Files in this item
| Files | Description | Format |
|---|---|---|
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application/pdf  B51-DAC_1.pdf (26MB) | (no description provided) |
Description
| Title: | Delay Modeling of Bipolar ECL/EFL Circuits |
| Author(s): | Yang, Andrew Tien |
| Subject(s): | Delay modeling
Bipolar circuits ECL/EFL transistor circuits Emitter-coupled logic Emitter-follower logic Timing simulation Digital circuits |
| Issue Date: | 1986-08 |
| Publisher: | Coordinated Science Laboratory |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-86-2222, DAC-1 |
| Genre: | Report |
| Type: | Text |
| Language: | English |
| Description: | Coordinated Science Laboratory was formerly known as Control Systems Laboratory |
| URI: | http://hdl.handle.net/2142/75361 |
| Sponsor: | Joint Services Electronics Program / N000-14-84-C-0149 |
| Date Available in IDEALS: | 2015-04-22 |