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Title:Switch-Level Test Generation for MOS VLSI Circuits
Author(s):Najm, Farid Nasri
Subject(s):Switch-level
MOS VLSI circuits
Test generation
Fault simulation
Physical failures
Race conditions
Hazards
Logic circuits
D-algorithm
Combinatorial circuits
Test vectors
Issue Date:1986-08
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-86-2223, DAC-2
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/75363
Sponsor:Semiconductor Research Corporation / SRC RSCH 84-06-049-5
Date Available in IDEALS:2015-04-22
2017-07-15


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