Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  B51-DAC_26.pdf (30MB) | (no description provided) |
Description
| Title: | A Switch-Level Concurrent Fault Simulator for MOS Circuits |
| Author(s): | Lee, Terry Ping-Chung |
| Subject(s): | Switch-level simulation
MOS VLSI circuits Concurrent fault simulation Transistor level faults Switch-level matrix algebra Fault models |
| Issue Date: | 1991-01 |
| Publisher: | Analog and Digital Circuits, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-91-2201, DAC-26 |
| Genre: | Report |
| Type: | Text |
| Language: | English |
| Description: | Coordinated Science Laboratory was formerly known as Control Systems Laboratory |
| URI: | http://hdl.handle.net/2142/75367 |
| Sponsor: | Semiconductor Research Corporation / SRC 88-DP-109 |
| Date Available in IDEALS: | 2015-04-22 2017-07-14 |