Files in this item

FilesDescriptionFormat

application/pdf

application/pdfB54-CRHC_00_01.pdf (27MB)Restricted to U of Illinois
(no description provided)PDF

Description

Title:Delay Fault Testing for Enhanced Full Scan Based Circuits
Author(s):Sharma, Manish
Subject(s):Delay fault testing
Linear relationships
Basis path set
Segment delay fault model
Automatic test pattern generation
Issue Date:2000-06
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-00-2206, CRHC-00-01
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/75380
Sponsor:Semiconductor Research Corporation / SRC 99-TJ-717
DARPA
Hewlett Packard
Date Available in IDEALS:2015-04-22


This item appears in the following Collection(s)

Item Statistics