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Title:Architecture for Multiple Instruction Stream LSI Processors
Author(s):Kaminsky, William Joseph, Jr.
Subject(s):Pipelining
Precedence graph
Multiprocess
Issue Date:1977-10
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG 77-2243, R-796
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory changed its name from Control Systems Laboratory
URI:http://hdl.handle.net/2142/75628
Sponsor:Joint Services Electronics Program / DAAB-07-72-C-0259
National Science Foundation / MCS 73-03488 A01
Date Available in IDEALS:2015-04-22


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