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Title:Switch-Level Timing Simulation of MOS VLSI Circuits
Author(s):Rao, Vasant Bangalore
Subject(s):Switch-level simulation
Timing simulation
NMOS circuits
Delay operation
Graph algorithm
Issue Date:1985-01
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG 85-2207, R-1032
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory changed its name from Control Systems Laboratory
URI:http://hdl.handle.net/2142/75676
Sponsor:Joint Services Electronics Program / N00014-79-C-0424 and N00014-84-C-0149
IBM Corporation
Date Available in IDEALS:2015-04-22


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