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Description
Title: | Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths |
Author(s): | Vissa, Pranay |
Department / Program: | Electrical & Computer Eng |
Discipline: | Electrical & Computer Engr |
Degree Granting Institution: | University of Illinois at Urbana-Champaign |
Degree: | M.S. |
Genre: | Thesis |
Subject(s): | high-level synthesis
automation error detection scheduling binding optimization pipelining modulo arithmetic logic optimization state machine datapath shadow logic low cost high performance electrical faults Aliasing stuck-at faults soft errors timing errors checkpointing rollback recovery |
Abstract: | With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy techniques with 2x and 3x area cost eliminate the area reduction benefits of such scaling. In this study, we take a partial redundancy approach to the reliability problem for arithmetic-orientated datapaths by performing lightweight shadow computations in the mod-b space, where b is the base of our modulo residue, for each main computation. We leverage the binding and scheduling flexibility of high-level synthesis to detect control errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-b reducer sharing. We introduce logic and dataflow optimizations to further reduce cost. We evaluated our technique with 12 high-level synthesis benchmarks from the arithmetic- oriented PolyBench benchmark suite using FPGA emulated netlist-level error injection. When b = 3, we observe coverages of 99.2% for stuck-at faults, 99.5% for soft errors, and 99.8% for timing errors with a 25.7% area cost and negligible performance impact. When b = 5, we observe coverages of 99.4% for stuck-at faults, 99.8% for soft errors, and 99.9% for timing errors with a 48.5% area cost and negligible performance impact. Leveraging a mean error detection latency of 13.92 and 14.96 cycles, with both mod-3 and mod-5 units respectively (2554x faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0% for both cases, observing 411x increase in reliability against soft errors. |
Issue Date: | 2015-05-01 |
Type: | Thesis |
URI: | http://hdl.handle.net/2142/78571 |
Rights Information: | Copyright 2015 Pranay Vissa |
Date Available in IDEALS: | 2015-07-22 |
Date Deposited: | May 2015 |
This item appears in the following Collection(s)
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Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering -
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois