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Title:Pooled Dram with Direct Interconnect to Memory Controller
Author(s):Gardner, Conor
Contributor(s):Caesar, Matthew; Tahir, Rashid
Subject(s):RAM
DRAM
DDR3
240-pin
Sharing
FPGA
Load Balance
Swap
Abstract:During normal operation, a cluster of computers containing multiple nodes may suffer the following problem: one of the nodes will have a large workload and must resort to using slow swap memory from the hard disk when it runs out of RAM. At the same time, another compute node on the same server rack may be underloaded and have significant amounts of unallocated RAM. The proposed solution outlined by this paper is to build a device which plugs directly into the standard 240-pin DDR3 socket of a motherboard and behaves exactly like a normal DDR3 module from the memory controller's perspective. This module would contain some on-board RAM just like a normal memory module but would have the added feature of being networked with other identical modules on other nodes. This setup would allow each compute node to utilize local on-board RAM first but would also allow modules to borrow memory from each other when there is a severe load imbalance.
Issue Date:2015-05
Genre:Other
Type:Other
Language:English
URI:http://hdl.handle.net/2142/78989
Date Available in IDEALS:2015-08-03


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