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Title:High-Resolution Nyquist -Rate Analog -to -Digital Converter
Author(s):Chen, Hsin-Shu
Doctoral Committee Chair(s):Song, Bang-Sup
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Abstract:This thesis presents a pipelined analog-to-digital converter (ADC) employing a capacitor error-averaging technique with look-ahead decision and digital error correction concepts that has been implemented in a CMOS technology to achieve high linearity and high speed. The capacitor error-averaging technique can perform an accurate multiply-by-two (x2) function required in high-resolution pipelined ADCs, while a high gain op-amp has been designed to minimize error due to finite DC gain. Three clock phases are required by the capacitor error-averaging technique (rather than the conventional two clock phases), and the look-ahead decision technique takes advantage of this by allowing the residue amplifiers a full clock phase of settling time (rather than a partial clock phase in a conventional pipelined ADC). The fully differential pipelined ADC achieves a throughput rate of 20 Msamples/s and a linearity of 14 b without any type of trimming or calibration. The prototype ADC, fabricated in a double-poly triple-metal 0.5-mum CMOS process, exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The chip occupies an active area of 10.8 mm 2 including digital logic, output buffers, and bond pads, and consumes 720 mW at 5 V.
Issue Date:2001
Description:118 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001.
Other Identifier(s):(MiAaPQ)AAI3017039
Date Available in IDEALS:2015-09-25
Date Deposited:2001

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