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Title:High-Speed, Low-Spurious CMOS Analog -to -Digital Converter
Author(s):Choe, Myung-Jun
Doctoral Committee Chair(s):Song, Bang-Sup
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:Pipelining not only provides a speed advantage, but also enables the application of background offset trimming to folding ADCs. Background offset trimming with a delta-sigma modulator is applied to compensate the random input offset of folding amplifiers. A subranging front-end is used in conjunction with the pipelined folding ADC to make the calibration feasible. The second prototype chip was measured to exhibit 40 Msamples/s conversion rate with 13-bit resolution, consuming 800 mW at 5 V.
Issue Date:2001
Type:Text
Language:English
Description:96 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001.
URI:http://hdl.handle.net/2142/80747
Other Identifier(s):(MiAaPQ)AAI3030420
Date Available in IDEALS:2015-09-25
Date Deposited:2001


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