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Description
Title: | High-Speed, Low-Power 54-B X 54-B Digital Multiplier Architecture Using Redundant Binary |
Author(s): | Kim, Yun H. |
Doctoral Committee Chair(s): | Song, Bang-Sup |
Department / Program: | Electrical Engineering |
Discipline: | Electrical Engineering |
Degree Granting Institution: | University of Illinois at Urbana-Champaign |
Degree: | Ph.D. |
Genre: | Dissertation |
Subject(s): | Engineering, Electronics and Electrical |
Abstract: | A new architecture for a carry-free multiplier is proposed that focuses on redundant binary (RB) numbers and conversion techniques. By incorporating the Booth algorithm along with RB numbers, a pair of 2's complement input words can be multiplied in RB domain free of carry propagation. Using the proposed equivalent bit conversion algorithm (EBCA), the resulting RB product can be converted to a normal binary (NB) product in constant time regardless of word width. A prototype 54-b x 54-b multiplier is implemented using transmission gate logic circuits to prove the concept and algorithms of the proposed architecture. The proposed multiplier fabricated in 0.35 mum CMOS process is tested to operate at 74 MHz with 3.3 V power supply while consuming 53.4 mW of power. The proposed architecture of the carry-free multiplier is an ideal architectural candidate for low-power, high-speed, portable devices. |
Issue Date: | 2001 |
Type: | Text |
Language: | English |
Description: | 103 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001. |
URI: | http://hdl.handle.net/2142/80749 |
Other Identifier(s): | (MiAaPQ)AAI3030447 |
Date Available in IDEALS: | 2015-09-25 |
Date Deposited: | 2001 |
This item appears in the following Collection(s)
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Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering -
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois