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Title:Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology
Author(s):Jung, Seong-Ook
Doctoral Committee Chair(s):Kang, Sung-Mo (Steve)
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:Domino logic is known to consume more dynamic power than static logic. Low-voltage swing clock domino logic family is developed for substantial dynamic power saving. Delay-constrained power optimization algorithm allocates low supply voltage to logic gates such that dynamic power is minimized with timing constraint. Timing accuracy is ensured by accounting for timing variations due to gate-to-source voltage and input arrival time difference.
Issue Date:2002
Type:Text
Language:English
Description:125 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002.
URI:http://hdl.handle.net/2142/80764
Other Identifier(s):(MiAaPQ)AAI3044130
Date Available in IDEALS:2015-09-25
Date Deposited:2002


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