Crosstalk Noise in Deep Submicron Integrated Circuit Design

Abstract

Crosstalk noise has become a critical design and verification challenge for high-performance integrated circuits in deep submicron technologies. This thesis addresses crosstalk noise at methodological and algorithmic levels at various stages of the physical design flow. It proposes a signal integrity management physical design flow, underlining the changes required in the traditional design flow. Novel algorithms and methodologies are presented in this flow from early noise prevention to accurate and effective noise analysis to postroute noise reduction. Proposed algorithms, techniques and methodologies are evaluated in a system on chip (SoC) context, and several observations and guidelines are presented on the block, platform and chip level design phases of SoC designs. Results are given on several industrial, high-performance 0.13 mum--0.18 mum designs.