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Title:VLSI Architectures for Iterative Channel Decoders
Author(s):Mansour, Mohammad Monzer
Doctoral Committee Chair(s):Shanbhag, Naresh R.
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Abstract:Decoder architectures for LDPC codes introduce another complexity dimension related to the on-chip interconnect bottleneck of LDPC decoders. A new parameterized-core-based design methodology targeted for scalable and programmable LDPC decoders is proposed. The methodology solves the problems of excessive memory overhead, high latency, and complex on-chip interconnect typical of existing decoder implementations, which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels. The methodology proposes: (1) The concept of architecture-aware LDPC code design that solves the interconnect bottleneck, (2) a faster and memory-efficient turbo-decoding algorithm for LDPC codes, and a reduced-complexity mechanism for message computations, (3) a programmable, scalable, and code-rate tunable architecture platform, and (4) a core-generator for high performance decoders. A decoder chip has been implemented using this methodology in 0.18 mum technology, which delivers a throughput of 1.6 Gbps at 125 MHz and consumes 760 mW of power.
Issue Date:2003
Description:215 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003.
Other Identifier(s):(MiAaPQ)AAI3086131
Date Available in IDEALS:2015-09-25
Date Deposited:2003

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