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Title:Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests
Author(s):Sharma, Manish
Doctoral Committee Chair(s):Patel, Janak H.
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:We use circuit delay bounding based on a set of linear constraints, obtained from testing some paths in the circuit robustly, to investigate how well such tests cover distributed delay defects. Unfortunately, our experimental results using the above method show robust tests may not cover distributed delay defects very well.
Issue Date:2003
Type:Text
Language:English
Description:108 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003.
URI:http://hdl.handle.net/2142/80842
Other Identifier(s):(MiAaPQ)AAI3101968
Date Available in IDEALS:2015-09-25
Date Deposited:2003


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