Files in this item

FilesDescriptionFormat

application/pdf

application/pdf3153241.pdf (5MB)Restricted to U of Illinois
(no description provided)PDF

Description

Title:Noise -Tolerant Digital System Design
Author(s):Balamurugan, Ganesh
Doctoral Committee Chair(s):Naresh Shanbhag
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:In addition to ISI, jitter also limits performance in high-speed I/O links. A discrete-time model that comprehends both transmit and receive jitter is presented. Typical I/O channels are shown to amplify high-frequency transmit jitter limiting the performance of equalization and multilevel signaling schemes. Design techniques to mitigate the effect of jitter are also presented.
Issue Date:2004
Type:Text
Language:English
Description:120 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.
URI:http://hdl.handle.net/2142/80871
Other Identifier(s):(MiAaPQ)AAI3153241
Date Available in IDEALS:2015-09-25
Date Deposited:2004


This item appears in the following Collection(s)

Item Statistics