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Title:Algorithms and Architectures for Joint Equalization and Decoding
Author(s):Lee, Seok-Jun
Doctoral Committee Chair(s):Shanbhag, Naresh R.; Singer, Andrew C.
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:Various linear turbo equalizer VLSI architectures are explored. Energy-efficient architectures that eliminate redundant operations and employing early termination achieve power savings up to 60%. To improve the throughput, a concurrent processing VLSI architecture is proposed, where SISO equalizers and decoders are running concurrently, thereby increasing throughput by up to 75%. To improve the BER further, a class of switching linear turbo equalizers is also shown along with several feasible switching schemes.
Issue Date:2004
Type:Text
Language:English
Description:142 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.
URI:http://hdl.handle.net/2142/80893
Other Identifier(s):(MiAaPQ)AAI3160911
Date Available in IDEALS:2015-09-25
Date Deposited:2004


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