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Title:Dynamic Rate Controlled Input -Buffered Switch System With QoS
Author(s):Park, Sueng-Yong
Doctoral Committee Chair(s):Steve (sung-Mo) Kong
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Abstract:In the dissertation, we propose a new scheduling algorithm, dynamic rate controlled input output (DRCIO), which addresses the scalability and the implementability for a highly distributed high speed router. We developed the algorithm based on a Washington University (WASU) high speed switch. We first review the relationship between the queuing mechanism and the scheduling algorithm. We discuss the importance of the proper queuing mechanism for a router to be scalable. And we explain the in detail the measurement based backlog estimation for the distributed packet scheduling algorithm. We show that the complexity of this method is O(1) to calculate the total backlog, which is a significant improvement as it normally takes O( V), where V is the number of flows in a router. We also review the risks of inaccuracy when we resort to this O( 1) method. To prove the robustness of the DRCIO, we review the operation of the DRCIO in several boundary conditions, and show that the algorithm is robust enough to recover from any boundary or erroneous conditions.
Issue Date:2004
Description:132 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.
Other Identifier(s):(MiAaPQ)AAI3160938
Date Available in IDEALS:2015-09-25
Date Deposited:2004

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