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Title:Critical Branches and Lucky Loads in Control-Independence Architectures
Author(s):Malik, Kshitiz
Doctoral Committee Chair(s):Matthew Frank
Department / Program:Electrical and Computer Engineering
Discipline:Electrical and Computer Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Abstract:I perform a thorough analysis of the performance sensitivity of CI processors to disambiguation and forwarding. The insights from this analysis are used to drive the design of hardware mechanisms to perform these two functions that are low in complexity and yet attain high performance. The basic premise behind these mechanisms is to use small caches to perform early disambiguation and forwarding. These caches are not responsible for ensuring correctness; they merely enable high performance in the presence of lucky loads. The caches are backed up by a simple load re-execution mechanism that guarantees correctness. I find that the performance of a CI processor with small (32-entry and 128-entry) structures for disambiguation and forwarding, respectively, is within 10% of global load and store queues in the worst case.
Issue Date:2009
Description:148 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009.
Other Identifier(s):(MiAaPQ)AAI3392207
Date Available in IDEALS:2015-09-25
Date Deposited:2009

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