Files in this item

FilesDescriptionFormat

application/pdf

application/pdf9834687.pdf (3MB)Restricted to U of Illinois
(no description provided)PDF

Description

Title:New Techniques to Verify Timing Correctness of Integrated Circuits
Author(s):Heragu, Keerthinarayan Prasanna
Doctoral Committee Chair(s):Patel, Janak H.
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Computer Science
Abstract:A preliminary study of the relationship between false paths and delay fault testing is also presented. We first show an example where a circuit that does not have any delay variations behaves incorrectly during normal operation due to the common assumptions on false paths used in determining the clock cycle time. We then show an example of a faulty circuit that passes testing because certain false paths contribute to the invalidation of delay tests generated under a single-fault assumption. Finally, we show an example where a good circuit that functions correctly under normal operation is declared as faulty when certain false paths are activated during scan-based testing. For each case, we suggest possible remedies that can sometimes result in more conservative estimates on clock cycle times.
Issue Date:1998
Type:Text
Language:English
Description:111 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.
URI:http://hdl.handle.net/2142/81224
Other Identifier(s):(MiAaPQ)AAI9834687
Date Available in IDEALS:2015-09-25
Date Deposited:1998


This item appears in the following Collection(s)

Item Statistics