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Title:High-Level Testability Analysis and Enhancement for Digital Systems
Author(s):Hsu, Frank Fu-Chang
Doctoral Committee Chair(s):Patel, Janak H.
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Computer Science
Abstract:The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively represent the testability of the design. During testability evaluation, a subset of the variables listed in the high-level description is made fully controllable and observable to maximize the testability grading of the design. Then the registers that correspond to the selected variables are placed onto the scan-chain for partial-scan implementation. Experimental results show that the testability grading does correlate to the actual testability of circuits, and our technique produces partial-scan implementations that achieve better fault coverage compared to conventional gate-level selection techniques.
Issue Date:1998
Description:91 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.
Other Identifier(s):(MiAaPQ)AAI9912272
Date Available in IDEALS:2015-09-25
Date Deposited:1998

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