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Title:Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors
Author(s):Bellas, Nikolaos
Doctoral Committee Chair(s):Ibrahim Hajj
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Energy
Abstract:More specifically, we propose a technique that uses an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of the main power consumers in most of today's high-performance microprocessors. Results are reported for the SPEC95 benchmarks in the R-4400 processor which implements the MIPS2 instruction set architecture.
Issue Date:1999
Type:Text
Language:English
Description:114 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.
URI:http://hdl.handle.net/2142/81278
Other Identifier(s):(MiAaPQ)AAI9921661
Date Available in IDEALS:2015-09-25
Date Deposited:1999


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