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Title:The Monolithic Integration of Enhancement- and Depletion-Mode High Electron Mobility Transistors for Low-Power and High-Speed Circuit Applications in the Lattice -Matched Indium Phosphide Material System
Author(s):Mahajan, Aaditya
Doctoral Committee Chair(s):Adesida, Ilesanmi
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Abstract:By using a buried-Pt process in conjunction with proper heterostructure design, a procedure for the fabrication of enhancement-mode HEMTs (E-HEMTs) has been developed. Following the full characterization of E-HEMT devices, a heterostructure was then designed for the monolithic integration of E-HEMTs and D-HEMTs, using a two-level etch-stop process. Devices were successfully fabricated and characterized which showed the viability of a directcoupled FET logic (DCFL) circuit technology in the InP material system. To demonstrate the feasibility of this technology, DCFL ring oscillators were fabricated and tested. These circuits successfully demonstrated high-speed, low-power performance while utilizing only a single voltage supply.
Issue Date:1999
Description:121 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.
Other Identifier(s):(MiAaPQ)AAI9944931
Date Available in IDEALS:2015-09-25
Date Deposited:1999

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