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Title:Power and Voltage Drop Analyses in VLSI Circuits
Author(s):Yuan, Li-Pen
Doctoral Committee Chair(s):Kang, Sung-Mo (Steve)
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:The bottleneck of voltage drop analysis lies in the matrix inversion that is involved in solving the circuit equations of the power/ground bus. To remove the bottleneck, we proposed an algorithm to quickly estimate the cycle-by-cycle maximum voltage drop values of a circuit driven by an input sequence. Based on the rank of the estimates, a small set of input vectors is selected for detailed analysis to identify the worst-case voltage drop behavior. The pruning strategy has been applied to a set of industry designs and is found to be on average three times faster than direct network analysis. Compared to a straightforward approach of using the total power as the estimator, the proposed algorithm demonstrates higher run-time efficiency and better consistency with the actual simulation results.
Issue Date:1999
Type:Text
Language:English
Description:140 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.
URI:http://hdl.handle.net/2142/81301
Other Identifier(s):(MiAaPQ)AAI9945039
Date Available in IDEALS:2015-09-25
Date Deposited:1999


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