High-Speed, High-Precision Digital -Analog Converters Designed for Spectral Performance

Abstract

A number of chips have been realized in conventional CMOS processes to attain this goal. These chips share the common architectural feature of utilizing novel output stages coupled to a current-switching DAC to extract a high-linearity signal from the current- switched output. Provision is also made for static calibration to correct for current-source mismatch and attain the correct static linearity; this is also required for attaining the desired dynamic linearity. In the first prototype chip designed, the static calibration was in the form of a trim circuit external to the chip; in the second chip designed a novel self-trimming circuit which implements true background calibration was integrated on the die. For the first chip designed, at 60 MS/s, DAC spurious-free dynamic range (SFDR) was 80 dB for 5.1-MHz input signals and fell to only 75 dB for 25.5-MHz input signals. The second chip exhibited an SFDR of 82 dB falling to 72 dB over the Nyquist baseband at 100 MS/s, and an SFDR of 71 dB falling to 50 dB at 200 MS/s.