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Title:Crosstalk Noise and Timing Analysis of Digital VLSI Circuits With Coupled Interconnects
Author(s):Lu, Ninglong
Doctoral Committee Chair(s):Hajj, Ibrahim N.
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Abstract:At the logic hierarchical level, we have developed a logic-level timing analyzer that will perform static timing simulation as well m coupling noise estimation using the information produced during the circuit hierarchy stage. The results of this analyzer consist of (a) critical path delay for the entire circuit, (b) transition windows, and (c) crosstalk noises for all victim gates. The maximum amplitude and effective width of crosstalk can be obtained at the fan-out of each victim gate and used to check the failure criteria of the gate that receives this noise pulse as an input.
Issue Date:2000
Description:109 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000.
Other Identifier(s):(MiAaPQ)AAI9990067
Date Available in IDEALS:2015-09-25
Date Deposited:2000

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