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Title:Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors
Author(s):Tiwari, Abhishek
Doctoral Committee Chair(s):Torrellas, Josep
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Computer Science
Abstract:To address this problem, we show how to hide the effects of aging and slow it down. Our framework is called Facelift. It hides aging through aging-driven application scheduling. It slows down aging by applying voltage changes at key times---it uses a non-linear optimization algorithm to carefully balance the impact on the aging rate and on the critical path delays. Moreover, it can gainfully configure the chip for a short lifetime. We can take a multicore with a 7-year lifetime and, by hiding and slowing down aging, enable it to cycle, on average, at a 14--15% higher frequency. Alternatively, we can design a multicore for a 5 to 7-month lifetime and use it for 7 years.
Issue Date:2008
Description:105 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2008.
Other Identifier(s):(MiAaPQ)AAI3337941
Date Available in IDEALS:2015-09-25
Date Deposited:2008

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