Files in this item



application/pdf3363030.pdf (3MB)Restricted to U of Illinois
(no description provided)PDF


Title:Tradeoffs in Designing Massively Parallel Accelerator Architectures
Author(s):Mahesri, Aqeel A.
Doctoral Committee Chair(s):Patel, Sanjay J.
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Computer Science
Abstract:We propose a methodology for performing an integrated optimization of both the micro-architecture and the physical circuit design of the cores and caches. In our approach, we use statistical sampling of the design space for evaluating the performance of the micro-architecture and RTL synthesis to characterize the area-power-delay of the underlying circuits. This integrated methodology enables a much more powerful analysis of the performance-area and performance-power tradeoffs for the low level micro-architecture. We use this methodology to find the optimal design points for an accelerator architecture under area constraints and power constraints. Our results indicate that more complex architectures scale well in terms of performance per area, but that the addition of a power constraint favors simpler architectures.
Issue Date:2009
Description:152 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009.
Other Identifier(s):(MiAaPQ)AAI3363030
Date Available in IDEALS:2015-09-25
Date Deposited:2009

This item appears in the following Collection(s)

Item Statistics