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Title:The Retiming and Routing of VLSI Circuits
Author(s):Saxena, Prashant
Doctoral Committee Chair(s):Liu, C.L.
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Mathematics
Abstract:Multi-layer technologies present additional challenges to the routing of the nets because the layer assignment can have a large impact on the net delays. Traditional approaches cause the first few nets to monopolize the "good" layers. Therefore, they perform poorly under the metric of minimizing the maximum net delay. We propose the use of dynamic area quotas to remedy this problem. Our approach is independent of the routing model and the router used, and works very well in practice.
Issue Date:1998
Type:Text
Language:English
Description:78 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.
URI:http://hdl.handle.net/2142/81934
Other Identifier(s):(MiAaPQ)AAI9912369
Date Available in IDEALS:2015-09-25
Date Deposited:1998


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