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Title:Power Estimation and Minimization of Digital Signal Processing Systems
Author(s):Ramprasad, Sumant
Doctoral Committee Chair(s):Naresh Shanbhag; Ibrahim Hajj
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:We have so far focussed on power dissipation in static CMOS circuits. Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. In this thesis, we also present an optimization technique, termed clock-generating (CG) domino, for dual-output domino logic that reduces area, dock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output.
Issue Date:1999
Type:Text
Language:English
Description:136 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.
URI:http://hdl.handle.net/2142/81947
Other Identifier(s):(MiAaPQ)AAI9944976
Date Available in IDEALS:2015-09-25
Date Deposited:1999


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