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Title:Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Author(s):Hamzaoglu, Ilker
Doctoral Committee Chair(s):Patel, Janak H.
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:Finally, we propose a new synthesis technique for reducing the test application time of counter-based exhaustive built-in-self-test test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the counter-based test pattern generators.
Issue Date:1999
Type:Text
Language:English
Description:138 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.
URI:http://hdl.handle.net/2142/81957
Other Identifier(s):(MiAaPQ)AAI9953037
Date Available in IDEALS:2015-09-25
Date Deposited:1999


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