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Title:Layout Extraction Including Substrate Parasitics for ESD Protection Circuits and Design Rule Checking
Author(s):Li, Qiao
Doctoral Committee Chair(s):Sun-Mo (Steve) Kang
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Abstract:ESD design rule checking is different from the conventional design rule checking in that not only different rules have to be applied for different components in the ESD protection circuit, but also style of layout is of utmost importance to ensure uniform current distribution during ESD events. ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified.
Issue Date:2001
Description:121 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001.
Other Identifier(s):(MiAaPQ)AAI9996651
Date Available in IDEALS:2015-09-25
Date Deposited:2001

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