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Title:Selective lateral nano-epitaxy for manufacturable nanowire electronics
Author(s):Zhang, Chen
Director of Research:Li, Xiuling
Doctoral Committee Chair(s):Li, Xiuling
Doctoral Committee Member(s):Feng, Milton; Lyding, Joseph W.; Rogers, John A.
Department / Program:Electrical & Computer Engineering
Discipline:Electrical & Computer Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):III-V
vapor-liquid-solid (VLS) growth
selective lateral epitaxy
planar nanowire
Gallium Arsenide (GaAs)
Indium Arsenide (InAs)
metal–oxide–semiconductor field-effect transistor (MOSFET)
Abstract:This dissertation provides a comprehensive study on vapor-liquid-solid (VLS) growth of III-V planar nanowires and their electronic device applications. III-V materials, especially high-In-content InGaAs, are considered as a very promising n-channel material candidate for post-Si complementary metal-oxide-semiconductor (CMOS) technology due to their excellent electron mobility. Semiconductor nanowires are of interest for electronic device applications primarily due to their 3D nature which facilitates realization of multi-gate field effect transistors (FETs). VLS growth, where a metallic seed nanoparticle is used to gather materials and guide nanowire growth, is a unique bottom-up method suitable for synthesizing extremely thin nanowires with high aspect ratios and axially uniform diameters. Unlike conventional VLS nanowires which grow along out-of-plane directions with respect to the substrate surface, the recently emerged planar VLS growth produces III-V nanowires self-aligned along certain in-plane crystal directions and epitaxially attached to substrates. This particular type of VLS growth is called Selective Lateral nano-Epitaxy (SLE), where the selectivity is provided by seed nanoparticles. Those planar nanowires are compatible with the well-established planar processing technology and are therefore a potential solution to realizing manufacturable nanowire-based integrated circuits. In this dissertation, homogeneous GaAs planar nanowire arrays with perfect yield of planar growth, which are ready for practical device and circuit applications, are developed. The array-based GaAs planar nanowire growth also enables systematic growth studies, based on which the underlying mechanism responsible for the planar type of growth is proposed. In addition to homogeneous growth, heterogeneous SLE of high-quality planar InAs nanowires on GaAs is demonstrated. On the application side, GaAs planar nanowire tri-gate MOSFETs and a current-source loaded amplifier circuit based on nanowire MESFETs are presented. Gate-all-around (GAA) InAs planar nanowire MOSFETs are developed and analyzed. Chapter 1 discusses the motivation behind researching III-V materials and semiconductor nanowires for future low-power and high-performance nano-electronics. Chapter 2 introduces the planar type of VLS growth—Selective Lateral nano-Epitaxy—and compares it with the top-down nanowire fabrication technology. Chapter 3 presents the array-based GaAs planar nanowire growth and detailed growth mechanism studies intended to reveal the underlying reasons leading to the planar version of VLS growth. Chapter 4 demonstrates GaAs planar nanowire tri-gate n-MOSFETs with Al2O3 as gate dielectric material and a high voltage-gain amplifier circuit based on GaAs planar nanowire MESFETs. Chapter 5 presents the growth and material characterizations of heterogeneous InAs planar nanowires on GaAs substrate. InAs nanowire GAA MOSFETs are then presented with detailed device analysis. Chapter 6 outlines several future research directions including InAs nanowire MOSFET performance improvement, heterogeneous InAs planar nanowire growth yield improvement, and heterogeneous integration of different types of nanowires.
Issue Date:2015-06-15
Type:Thesis
URI:http://hdl.handle.net/2142/88143
Rights Information:Copyright 2015 Chen Zhang
Date Available in IDEALS:2015-09-29
Date Deposited:August 201


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