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Title:Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails
Author(s):Ho, Aaron Daniel
Advisor(s):Pilawa-Podgurski, Robert C.
Department / Program:Electrical & Computer Engineering
Discipline:Electrical & Computer Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):complementary metal–oxide–semiconductor (CMOS) integrated circuits
digital control
low-power electronics
power convertors
asymmetric interleaving
digital control
heterogeneous power rails
low voltage complementary metal–oxide–semiconductor (CMOS) power management
multiphase (complementary metal–oxide–semiconductor) CMOS power management IC system
multiphase power converters
multiple supply rails
reduced input current ripple
size 180 nm
Hardware
Mathematical model
Prototypes
Table lookup
Time-domain analysis
Abstract:Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will utilize symmetric interleaving as a method of reducing the input current ripple for the power converter. Asymmetric interleaving is a method of control that allows for a further reduction, and in some cases complete cancellation, of this input current ripple. This work looks at some of the challenges for a practical implementation using digital control, and provides results to quantify this improvement. This work demonstrates a control algorithm implementation capable of achieving nearly 3x reduction in the input current ripple via the asymmetric interleaving method.
Issue Date:2015-07-21
Type:Thesis
URI:http://hdl.handle.net/2142/88219
Rights Information:Copyright 2015 Aaron Daniel Ho
Date Available in IDEALS:2015-09-29
Date Deposited:August 201


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