Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  B61-UILU-ENG-94-2233-CRHC-94-18_opt.pdf (2MB) | (no description provided) |
Description
| Title: | Enhancing Testability of VLSI Circuits Using Partial Reset Techniques |
| Author(s): | Mathew, Ben |
| Subject(s): | Computer-aided design
VLSI Testability schemes Partial reset Sequential circuits Overhead Unrestricted at-speed |
| Issue Date: | 1994-08 |
| Publisher: | Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-94-2233, CRHC-94-18 |
| Genre: | Report (Grant or Annual) |
| Type: | Text |
| Language: | English |
| URI: | http://hdl.handle.net/2142/88478 |
| Sponsor: | Semiconductor Research Corp. |
| Date Available in IDEALS: | 2015-12-10 2017-07-15 |