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Title:New Techniques to Verify Timing Correctness of Integrated Circuits
Author(s):Heragu, Keerthinarayan Prasanna
Subject(s):Delay fault testing
Timing analysis
Fault model
Test generation
Issue Date:1997-12
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report No. UILU-ENG-97-2233, CRHC-97-18
Genre:Report
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88507
Sponsor:Semiconductor Research Corp. and DARPA; 96-DP-109 and DABT63-95-C-0069
Hewlett-Packard
Date Available in IDEALS:2015-12-10


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