Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  B61-UILU-ENG-97-2234-CRHC-97-19_opt.pdf (3MB) | (no description provided) |
Description
| Title: | Efficient Equivalence Checking in a Modular Design Environment |
| Author(s): | Hasteer, Gagan |
| Subject(s): | Equivalence checking
Modular design Steady states Sequential hardware equivalence Interface verification Safety property Multi-phase design methodology Minimum area retiming |
| Issue Date: | 1997-12 |
| Publisher: | Coordinated Science Laboratory |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-97-2234, CRHC-97-19 |
| Genre: | Report |
| Type: | Text |
| Language: | English |
| URI: | http://hdl.handle.net/2142/88508 |
| Sponsor: | DARPA / DAAH04-94-G-0273 |
| Date Available in IDEALS: | 2015-12-10 2017-07-15 |