Files in this item
Files | Description | Format |
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application/pdf ![]() ![]() | Full text |
Description
Title: | Efficient Equivalence Checking in a Modular Design Environment |
Author(s): | Hasteer, Gagan |
Subject(s): | Equivalence checking
Modular design Steady states Sequential hardware equivalence Interface verification Safety property Multi-phase design methodology Minimum area retiming |
Issue Date: | 1997-12 |
Publisher: | Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-97-2234, CRHC-97-19 |
Genre: | Report (Grant or Annual) |
Type: | Text |
Language: | English |
URI: | http://hdl.handle.net/2142/88508 |
Sponsor: | DARPA / DAAH04-94-G-0273 |
Date Available in IDEALS: | 2015-12-10 2017-07-15 |