Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  88-2205.pdf (5MB) | Full Text |
Description
| Title: | The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms |
| Author(s): | Rogers, William Arthur |
| Subject(s): | Digital circuit design
Fault simulation Automatic test pattern generation Hierarchy in test generation Fault simulation Testability analysis algorithms |
| Issue Date: | 1988-01 |
| Publisher: | Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-88-2205, CSG-80 |
| Genre: | Report |
| Type: | Text |
| Language: | English |
| URI: | http://hdl.handle.net/2142/88600 |
| Sponsor: | SRC Hewlett-Packard Semiconductor Research Corporation (including SRC member companies Hewlett-Packard and General Electric) / SRC 87-DP-109 |
| Date Available in IDEALS: | 2015-12-10 2017-07-15 |