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Title:Performance Evaluation of Multiple Register Set Architectures and Cache Memories
Author(s):Eickemeyer, Richard James
Subject(s):Multiple register set architectures
Memory
Cache memory
Performance measurements
Issue Date:1988-01
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-88-2207, CSG-82
Genre:Report
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88602
Sponsor:Semiconductor Research Corp., 87-DP-109
Date Available in IDEALS:2015-12-10


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