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Title:Techniques to Speedup Test Generation for VLSI Circuits
Alternative Title:Techniques to Speed Up Test Generation for VLSI Circuits
Author(s):Chandra, Susheel Jagdish
Subject(s):Test generation
Logic circuits
Parallel processing
Mapping strategies
Issue Date:1989-09
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-89-2232, CSG-109
Genre:Report
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88609
Sponsor:Semiconductor Research Corporation / 88-DP-109
Date Available in IDEALS:2015-12-10


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