Files in this item

FilesDescriptionFormat

application/pdf

application/pdfB52-UILU-ENG-87-2279 -DAC-8_opt.pdf (3MB)Restricted to U of Illinois
(no description provided)PDF

Description

Title:Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Author(s):Tejayadi, Ongky
Subject(s):Timing simulation
Piecewise linear techniques
Dynamic partitioning
Parallel algorithms
VLSI
Issue Date:1987-12
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-87-2279, DAC-8
Genre:Report
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88611
Sponsor:Semiconductor Research Corporation / 86-12-109
Joint Services Electronics Program / N00014-84-C-0149
Date Available in IDEALS:2015-12-10


This item appears in the following Collection(s)

Item Statistics