Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  88-2208.pdf (3MB) | Full text |
Description
| Title: | Logic and Fault Simulation of VLSI Circuits Including Hierarchical Techniques |
| Author(s): | Saab, Daniel Georges |
| Subject(s): | Logic simulation
Fault simulation Switch-level models Hierarchical techniques VLSI circuits Parallel-concurrent fault simulation MOS circuits Bipolar circuits |
| Issue Date: | 1988-01 |
| Publisher: | Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-88-2208, DAC-10 |
| Genre: | Report |
| Type: | Text |
| Language: | English |
| URI: | http://hdl.handle.net/2142/88612 |
| Sponsor: | Semiconductor Research Corporation / SRC 86-12-109 TRW Corporation |
| Date Available in IDEALS: | 2015-12-10 2017-07-15 |