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Title:iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
Author(s):Gee, Perry
Subject(s):Synthesis
Cell generation
Physical layout
Symbolic layout
Metal-metal matrix
Logic design compaction
Delay optimization
Issue Date:1989-12
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-89-2243, DAC-16
Genre:Report
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88616
Sponsor:Joint Services Electronics Program / N00014-84-C-0149
Semiconductor Research Corporation / SRC 88-DP-109
Texas Instruments
Date Available in IDEALS:2015-12-10


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