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Description
Title: | Diagnosis and Correction of Logic Design Errors |
Author(s): | Chung, Pi-Yu |
Subject(s): | Logic design errors
Diagnosis Error correction Design verification Binary decision diagram (BDD) Error models VLSI circuits |
Issue Date: | 1993-11 |
Publisher: | Analog and Digital Circuits, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-93-2247, DAC-42 |
Genre: | Report (Grant or Annual) |
Type: | Text |
Language: | English |
URI: | http://hdl.handle.net/2142/88625 |
Sponsor: | Joint Services Electronics Program / N00014-90-J-1270 |
Date Available in IDEALS: | 2015-12-10 2017-07-14 |