Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  B52-UILU-ENG-94-2216 -DAC-46_opt.pdf (3MB) | (no description provided) |
Description
| Title: | Timing and Area Optimization for VLSI Circuit and Layout |
| Author(s): | Chuang, Wei-Tong |
| Subject(s): | Time-area optimization
VLSI layout Linear programming Delay estimation Sequential circuits Physical design Placement Gate sizing |
| Issue Date: | 1994-05 |
| Publisher: | Analog and Digital Circuits, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-94-2216, DAC-46 |
| Genre: | Report |
| Type: | Text |
| Language: | English |
| URI: | http://hdl.handle.net/2142/88628 |
| Sponsor: | Joint Services Electronics Program / N00014-90-J-1270 |
| Date Available in IDEALS: | 2015-12-10 2017-07-15 |