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Title:Parallel Processing for VLSI Simulation
Author(s):Mueller-Thuns, Robert Bernard
Subject(s):Gate-level logic
Fault simulation
Preprocessing
Synchronization
Switch-level simulation
Parallel framework
Issue Date:1990-08
Publisher:Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-90-2230, CRHC-90-2
Genre:Report
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88634
Sponsor:Semiconductor Research Corporation
Motorola, Inc.
Date Available in IDEALS:2015-12-10


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