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Title:Timing Verification and Synthesis of Circuits for Delay Fault Testability
Author(s):Roy, Kaushik
Subject(s):Testability
RTL
Transfer
Robust
Combinational logic circuit
Issue Date:1990-09
Publisher:Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-90-2244, CRHC-90-11
Genre:Report
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88640
Sponsor:Semiconductor Research Corporation / 89-DP-109
Texas Instruments
Date Available in IDEALS:2015-12-10


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