Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  B55-UILU-ENG-92-2208-CRHC-92-05_opt.pdf (3MB) | (no description provided) | |
|
application/pdf UILU-ENG-92-2208 pages 68 and 69.pdf (56kB) | Figures 4.8 and 4.9, which are missing from the main scan of this report |
Description
| Title: | Automatic Test Generation for Bit-serial VLSI Digital Signal Processors |
| Author(s): | Roy, Rabindra Kumar |
| Subject(s): | Signal processing
VLSI Hierarchical testing Test generation Bit-serial architecture |
| Issue Date: | 1992-02 |
| Publisher: | Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-92-2208, CRHC-92-05 |
| Genre: | Report |
| Type: | Text |
| Language: | English |
| URI: | http://hdl.handle.net/2142/88654 |
| Sponsor: | Semiconductor Research Corporation General Electric / expired gift |
| Date Available in IDEALS: | 2015-12-10 2017-07-15 |