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Title:Architectural Level Test Generation and Fault Simulation
Author(s):Lee, Jaushin
Subject(s):Automatic test pattern generation
Fault simulation
Circuit module diagram
Finite space searching
DFT
Issue Date:1992-10
Publisher:Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-92-2238, CRHC-92-20
Genre:Report
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88660
Sponsor:Semiconductor Research Corp. / 91-DP-109
Date Available in IDEALS:2015-12-10


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