Browse Dissertations and Theses - Electrical and Computer Engineering by Contributor "Patel, Janak H."

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  • Lee, Jaushin (1992)
    In this thesis, a high level branch-and-bound based ATPG approach will be first presented. This method is a reasonable extension of the gate level ATPG approaches. Although various effective techniques have been applied, ...

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  • Roy, Rabindra Kumar (1992)
    Linear digital signal processors, commonly implemented using silicon compilers in bit-serial architecture, are very difficult to test for manufacturing defects due to deep sequentiality, low controllability and observability, ...

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  • Simonson, Jonathan (1996)
    Dependable real-time systems are essential to time-critical applications. The systems that run these applications require high degrees of performance and predictability. Although memory caching has long been known as a ...

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  • Cheong, Hoichi (1990)
    The cache coherence maintenance problem has been the major obstacle in using private cache memory to reduce memory access latency in large-scale multiprocessor systems. Two compiler-directed solutions, the fast selective ...

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  • Chickermane, Vivekanand (1993)
    The increasing use of high-level description languages, such as VHDL, to design large VLSI circuits has opened up some interesting research possibilities. It is now feasible to locate hard-to-test areas of a large circuit ...

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  • Sharma, Manish (2003)
    We use circuit delay bounding based on a set of linear constraints, obtained from testing some paths in the circuit robustly, to investigate how well such tests cover distributed delay defects. Unfortunately, our experimental ...

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  • Cha, Hungse (1994)
    Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively ...

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  • Narain, Prakash (1992)
    The traditional approaches to test generation made use of the gate level representation of the circuit. This test generation problem is known to be NP-Complete for combinational circuits. A high level test generation ...

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  • Hsu, Frank Fu-Chang (1998)
    The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively ...

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  • Luo, Lijuan (2011-05-25)
    As the semiconductor industry marches towards 22 nm technology and beyond, circuit design has become unprecedentedly omplicated. This presents many new challenges for EDA (electronic design automation), such as lack of ...

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  • Lai, Liyang (2005)
    The dissertation investigates new techniques for logic built-in self-test (BIST) in VLSI chip testing. The main purpose of these techniques is to improve fault coverage for logic BIST with minimal performance penalty and ...

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  • Heragu, Keerthinarayan Prasanna (1998)
    A preliminary study of the relationship between false paths and delay fault testing is also presented. We first show an example where a circuit that does not have any delay variations behaves incorrectly during normal ...

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  • Choudhary, Alok Nidhi (1989)
    Computer vision has been regarded as one of the most complex and computationally intensive problems. An integrated vision system (IVS) is a system that uses vision algorithms from all levels of processing to perform for a ...

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  • Eickemeyer, Richard James (1988)
    Multiple register set architectures have been proposed as a method to reduce the large amount of memory traffic associated with high-level language procedure calls. In this thesis, the effect on overall processor memory ...

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  • Sartori, John (2012-09-18)
    As traditional approaches for reducing power in microprocessors are being exhausted, extreme power challenges call for unconventional approaches to power reduction. Recent research has shown substantial promise for ...

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  • Baxter, Jeffrey John (1992)
    In this thesis we explore the problem of resource management for multicomputer systems. A variety of algorithms were developed for different task graph models. We first present a suite of static resource management algorithms. ...

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  • Hsiao, Michael Shaun (1997)
    Finally, synchronizing sequences can greatly benefit test generation. Finding these sequences, however, is nontrivial. The GA is applied to find short synchronizing sequences, and applications of these sequences are also ...

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  • Rudnick, Elizabeth Marie (1994)
    Fault simulators are used extensively in the design of electronic circuits for both testing and fault diagnosis. Complex component types can be easily handled in a fault simulator, since processing occurs in the forward ...

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  • Niermann, Thomas Michael (1991)
    Test pattern generation has progressed to a stage at which automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. ...

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